A semiconductor memory device typically includes an array of memory cells arranged in rows and columns, with each memory cell configured to store one or more bits of data. The memory cells within a given row of the array are coupled to a common wordline, while the memory cells within a given column of the array are coupled to a common bitline. Thus, the array includes a memory cell at each point where a wordline intersects with a bitline.
In a semiconductor memory device of the type described above, data may be written to or read from the memory cells of the array using a memory cycle that is divided into a precharge phase and an active phase, with the precharge phase being used to precharge the bitlines to a precharge voltage, and the active phase being used to read or write one or more memory cells of the array. Reading a given memory cell generally comprises transferring data stored within that cell to its corresponding bitline, and writing a given memory cell generally comprises transferring data into that cell from its corresponding bitline.
Memory cell access time is becoming an increasingly important issue in memory device design. For example, excessive memory cell access times can lead to performance bottlenecks in high speed processors. Conventional approaches to reading data from a memory cell include the use of differential balanced sense amplifiers or single-ended unbalanced sense amplifiers. However, as transistor dimensions continue to shrink, such conventional approaches can become problematic at least in part due to local transistor mismatch in the sense amplifier circuitry.
An alternative approach to reading data from a memory cell is known as inverter sensing. In this approach, a given read bitline of the memory device is read directly using an inverter and associated logic circuitry. This approach has some significant advantages over the conventional sense amplifier approaches previously described. For example, it avoids the problems relating to local transistor mismatch. Also, the inverter sensing approach does not utilize a precharge phase, thereby allowing precharge circuitry and output latch logic to be eliminated. Inverter sensing circuitry can therefore operate at a lower voltage and reduced power relative to conventional sense amplifiers. Unfortunately, conventional inverter sensing can be slower than the sense amplifier approaches, particularly in memory devices in which both rising and falling bitline transitions are used to read data. Thus, memory access times may be unduly long when using conventional inverter sensing.